51 research outputs found

    Low-power clock distribution networks for 3-D ICs

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    Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce the power consumption while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. This paper, consequently, introduces a design methodology for resonant 3-D clock networks that lowers the power of the clock networks while supporting pre-bond test. Several 3-D clock network topologies are explored in a 0.18 ÎĽm CMOS technology. Simulation results indicate 43% reduction in the power consumed by the resonant 3-D clock network as compared to a conventional buffered clock network. By properly distributing the inductance within the layers of the 3-D stack, resonance is ensured both in pre-bond test and normal operation. The important aspects of this approach are introduced in this paper

    A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

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    Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional clock distribution schemes. These networks utilize ad- ditional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. This paper, consequently, introduces a design method- ology for resonant 3-D clock networks that supports wireless pre- bond testing through the use of inductive links. By employing the inductors comprising the LC tanks of the resonant clock net- works as the receiver circuit for the links, the need for additional circuits and/or interconnect resources during pre-bond test is essentially eliminated. The proposed technique produces low power and pre-bond testable 3-D clock distribution networks. Simulation results indicate 98.5% and 99% decrease in the area overhead and power consumed by the contactless testing method as compared to existing methods

    Angiogenesis in cancer of unknown primary: clinicopathological study of CD34, VEGF and TSP-1

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    BACKGROUND: Cancer of unknown primary remains a mallignancy of elusive biology and grim prognosis that lacks effective therapeutic options. We investigated angiogenesis in cancer of unknown primary to expand our knowledge on the biology of these tumors and identify potential therapeutic targets. METHODS: Paraffin embedded archival material from 81 patients diagnosed with CUP was used. Tumor histology was adenocarcinoma (77%), undifferentiated carcinoma (18%) and squamous cell carcinoma (5%). The tissue expression of CD34, VEGF and TSP-1 was assessed immunohistochemically by use of specific monoclonal antibodies and was analyzed against clinicopathological data. RESULTS: VEGF expression was detected in all cases and was strong in 83%. Stromal expression of TSP-1 was seen in 80% of cases and was strong in 20%. The expression of both proteins was not associated with any clinical or pathological parameters. Tumor MVD was higher in tumors classified as unfavorable compared to more favorable and was positively associated with VEGF and negatively with TSP-1. CONCLUSION: Angiogenesis is very active and expression of VEGF is almost universal in cancers of unknown primary. These findings support the clinical investigation of VEGF targeted therapy in this clinical setting

    Interconnect design tradeoffs for silicon and glass interposers

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    Timing-driven via placement heuristics for three-dimensional ICs

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    This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and sharing with colleagues. Other uses, including reproduction and distribution, or selling or licensing copies, or posting to personal, institutional or third party websites are prohibited. In most cases authors are permitted to post their version of the article (e.g. in Word or Tex form) to their personal website or institutional repository. Authors requiring further information regarding Elsevier’s archiving and manuscript policies are encouraged to visit

    Three-dimensional integrated circuit design

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    3-D topologies for networks-on-chip

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